1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly, to a configuration of a semiconductor integrated circuit device integrated with a test circuit for performing a test thereon.
2. Description of the Background Art
Most of semiconductor memory devices have spare memory cells and in a case where a defective memory cell exists in a part of normal memory cells, the defective memory cell can be replaced with a spare memory cell to save a defective chip.
On the other hand, in a field where especially high speed data processing such as image processing is requested, a semiconductor memory device and a logic circuit for performing an operation on data stored in the semiconductor memory device have been integrated on the same chip. This is because, in this configuration, a circuit portion of a semiconductor memory device, for example a dynamic random access memory (the dynamic random access memory is hereinafter referred to as a DRAM and the circuit portion thereof is hereinafter referred to as a DRAM core) and a logic circuit are connected by a bus with a large width therebetween and both circuits are arranged adjacent to each other, thereby, enabling data supplying/receiving to be performed at high speed to realize higher speed operation.
FIG. 43 is a schematic block diagram for describing a test operation on a semiconductor integrated circuit device 8000 integrated with a DRAM core 8010 and a logic circuit 8020.
Referring to FIG. 43, in a semiconductor integrated circuit device 8000, there is further provided a tester interface section 8030 supplying/receiving of data between DRAM core 8010 and an external tester 8100 in order that a test for detecting a defective bit in a DRAM core is performed with external tester 8100.
It is assumed that DRAM core 8010 and tester interface section 8030 integrated on semiconductor integrated circuit device 8000 are connected therebetween, for example, by an internal data bus having a 256 bit width. On the other hand, tester interface section 8030 and external tester 8100 are connected therebetween, for example, by an external data bus having an 8 bit width.
While in the interior of the chip, it is easy to increase a bus width of the internal data bus, that is the number of I/O, on the other hand a width of the external bus cannot be increased unlimitedly since the width relates to the number of pads and therefore, the number of pins for connecting semiconductor integrated circuit device 8000 with an external circuit.
Therefore, in a case where an analysis on a detective bit in DRAM core 8010 is performed with an external tester, it is required that the test is performed through an external data bus having a small width, having resulted in a problem of increase in a test time.
External tester 8100 sequentially performs writes of test data into memory cells in DRAM core 8010 through such a tester interface section 8030. Furthermore, external tester 8100 sequentially performs reads of data from DRAM core 8000 through tester interface section 8030 to test the presence or absence of a defective bit based on a comparison result between read data and an expected value of the read data.
Therefore, in order to perform the test on DRAM core 8010 at high speed, external tester 8100 is also required to be adapted to an operating speed of DRAM core 8010 operating at high speed, thereby also having lead to a problem of increase in a cost of the external tester, itself. In external tester 8100, a redundancy analysis is performed on what replacement process with combinations of redundant memory cell columns and redundant memory cell rows provided in DRAM core 8010 can realize saving on a detective bit that has been detected as described.
FIG. 44 is a schematic block diagram for describing a configuration of a semiconductor integrated circuit device 8200 integrated with a built-in self-test/redundancy saving analysis section 8230 in order to solve the problem in a test operation on DRAM core 8010 of semiconductor integrated circuit device 8000 in FIG. 43. A built-in self-test is hereinafter also abbreviated as xe2x80x9cBISTxe2x80x9d.
Semiconductor integrated circuit device 8200 includes: a DRAM core 8210, a logic circuit 8220 for performing a logic operation on data stored in DRAM core 8210; and built-in self-test/redundancy saving analysis section 8230 for detecting defective bits in DRAM core 8210 to analyze on what replacement process with combinations of redundant memory cell rows and redundant memory cell columns in DRAM core 8210 should be applied
A configuration of such a built-in self-test/redundancy saving analysis section 8230 is disclosed in, for example, Japanese Patent Laying-Open No. 2001-6387 or in a document, T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada and H. Hidaka, xe2x80x9cA Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMsxe2x80x9d, International Test Conference 2000 Proceedings, pp. 567-574.
Therefore, if built-in self-test/redundancy saving analysis section 8230 as shown in FIG. 44 is integrated on semiconductor integrated circuit device 8200, DRAM core 8210 and built-in self-test/redundancy saving analysis section 8230 can be connected therebetween by an internal data bus with a comparatively large bit width, for example a 256 bit I/O. Hence, Problems can be avoided of increase in test time and a cost required for an external tester device as described in FIG. 43.
For example, in a case where plural DRAM cores with different memory capacities are integrated on one chip, however, there arises a problem to be further solved as described below:
FIG. 45 is a schematic diagram for describing a configuration of a semiconductor integrated circuit device 8400 integrated with plural DRAM cores on one chip.
A first DRAM core 8410 and a second DRAM core 8440 are integrated on semiconductor integrated circuit device 8400. Provided to first DRAM core 8410 are: a logic circuit 8420 for supplying/receiving data with first DRAM core 8410 and performing a logic operation; and built-in self-test/redundancy saving analysis section 8430 for detecting a defective bit in first DRAM core 8410 and performing analysis for redundancy saving on first DRAM core 8410.
On the other hand, provided to second DRAM core 8440 are: a logic circuit 8450 for supplying/receiving data with second DRAM core 8440 and performing a logic operation; and a built-in self-testing/redundancy saving analysis section 8460 for detecting a defective bit in second DRAM core 8440 and performing analysis for redundancy saving on second DRAM core 8440.
Herein, it is assumed that a memory capacity of DRAM core 8440 is lager than that of DRAM core 8410.
Therefore, it is assumed that, for example, while DRAM core 8410 and built-in self-test/redundancy saving analysis section 8430 are connected therebetween by a 256 bit internal data bus. DRAM core 8440 and built-in self-test/redundancy saving analysis section 8460 are connected therebetween by an internal data bus with a width of 2048 bits.
Furthermore, in general, DRAM core 8410 and DRAM core 8440 are different from each other in the number of redundant memory cell rows and the number of redundant memory cell columns.
Based on such differences in memory capacity and configuration of redundant memory cells, a necessity arises that provided to DRAM core 8410 and DRAM core 8440 are built-in self-test/redundancy saving analysis section 8430 and built-in self-test/redundancy saving analysis section 8460, respectively, which are different from each other.
When, in such a manner, built-in self-test/redundancy saving analysis sections are provided to respective DRAM cores, there arise problems that an area penalty increases, thereby inviting increase in chip area.
It is an object of the present invention to provide a semiconductor integrated circuit integrated with a test circuit capable of flexibly adapting to not only a case where a change occurs in memory capacity of a DRAM core but a case where a change also occurs in the number of redundant memory cell rows and the number of redundant memory cell columns provided to a DRAM core.
The present invention will be summarized such that the present invention is directed to a semiconductor integrated circuit device, being provided with plural memory circuits and a redundancy replacement test circuit.
Each of the plural memory circuits includes a normal memory cell array having plural normal memory cells therein and a spare memory cell array having plural spare memory cell rows and plural spare memory cell columns therein.
The redundancy replacement test circuit is provided commonly to the plural memory circuits to determine a defective address to be repaired by replacement. The redundancy replacement test circuit includes a self-test circuit and a redundancy analysis circuit.
The self-test circuit generates address signals for sequentially selecting memory cells to detect a defective memory cell based on results of comparison between data read out from the memory cells and expected value data.
The redundancy analysis circuit determines a defective address on which replacement is to be performed with one of plural spare memory cell rows and plural spare memory cell columns according to an address signal from the self-test circuit and a detection result on the defective memory cell. The redundancy analysis circuit has an address storage circuit, a drive circuit and a determination circuit. The address storage circuit stores a defective address corresponding to a defective memory cell. The drive circuit limits an effective memory space of the address storage circuit according to a capacity of a memory circuit to be tested among the plural memory circuits and performs data storage into the address storage circuit. The determination circuit determines which of spare memory cell rows and spare memory columns the defective cell is replaced with according to a defective address stored in the address storage circuit. The address storage circuit selectively stores the defective address different from any of already stored detective row addresses and defective column addresses among sequentially detected defective addresses.
The address storage circuit preferably includes plural CAM cells (Content Addressable Memory Cells) arranged in matrix.
Furthermore, the determination circuit preferably comprises a plurality of replacement determination sections provided correspondingly to respective sequences of replacement steps. Each of the sequences of replacement steps corresponds to a sequence in which defective memory cell rows and defective memory cell columns are sequentially replaced with spare memory cell rows and spare memory cell columns in the memory circuit including the maximum number of spare memory cell rows and spare memory cell columns among the plurality of memory circuits.
Each of the plurality of replacement determination sections has a replacement sequence determination circuit and a determination step limit circuit. The replacement sequence determination circuit determines whether repair of defective memory cells is completed before reaching a final step among the sequence of replacement steps. The determination step limit circuit selectively sets one of the replacement steps as the final step according to the number of the spare memory cell rows and the spare memory cell columns belonging to the memory circuit to be tested among the plurality of memory circuits.
Alternatively, the semiconductor integrated circuit device further includes plural select circuits provided correspondingly to respective plural memory circuits and connected in series to each other. Write data to a memory circuit to be tested among the plural memory circuit is transmitted from a self-test circuit by a shifting operation sequentially passing through the plural select circuits.
Alternatively, the redundancy replacement test circuit further preferably includes: a first internal address generation circuit for generating an internal address for a test operation according to a capacity of a memory cell array of a memory circuit to be tested among the plural memory circuits. Each memory circuit further includes: a second internal address generation circuit generating an internal address for a test operation on a memory circuit in synchronism with the first internal address generation circuit based on an initial value given from said redundancy replacement circuit.
Therefore, an advantage of the present invention is that on a semiconductor integrated circuit device itself, there can be integrated a test circuit having a redundancy analysis function capable of performing detection of a defective memory cell and redundancy analysis on a comparatively small circuit scale even in a case where memory capacities of plural semiconductor memory circuits formed on the same chip are of respective values different from each other.
Another advantage of the present invention is that on a semiconductor integrated circuit device itself according to any of claims 3 and 7, there can be integrated a test circuit having a redundancy analysis function capable of performing detection of a defective memory cell and redundancy analysis on a comparatively small circuit scale even in a case where configurations of redundancy memory cells formed in respective plural semiconductor memory circuits integrated on the same chip are different from each other.
Still another advantage of the present invention is that a circuit configuration for supplying/receiving of data between a self-test circuit and a memory circuit to be tested can be simplified, thereby enabling a chip area to decrease.
Yet another advantage of the present invention is that since an addresses for a test is generated by each of a memory cell and a redundancy replacement test circuit, no necessity arise for transfer of an address from the redundancy replacement test circuit to the memory cell during the test, thereby enabling a test time to decrease.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.